1) Field of the Invention
This invention relates to the field of video processing and in particular to an integrated video processing system.
2) Background Art
In known digital video processing systems, it is conventional to store words on both word boundaries and on half word boundaries. Some devices within the system may be compatible with word boundary alignments while other devices may be compatible with half word alignments. Therefore, it is often necessary to swap half words in order to make one type of device compatible with an other.
It is know to determine, for example by means of the video processor itself, the expected alignment of data and the actual alignment of data. The video processor may then perform a swap as required according to these determinations. However, this process uses video processor capability which may be better used elsewhere in the video processor system.
It is also known for several different devices within a video processor system to provide interrupt output signals to other devices in the system. Some of these interrupt output signals are active high and some are active low. Additionally, some are driven with open drain output devices and some are driven with totem pole output devices. Some of these output devices are tristate and some are non tristate.
The interrupt receiving devices of these video processor systems are normally adapted to receive interrupt output signals only from devices having predetermined output characteristics. Thus, for example, a device which is compatible with active high interrupts will not operate properly if provided with interrupts that are active low. This type of incompatibility also arises with respect to open drain outputs and totem pole outputs as well as tri-state and non tri-state outputs. Therefore, devices which are not compatible for these reasons must be interfaced. This requires extra hardware in order to receive the interrupt output signal of one device and provide, in response to this received signal, an interrupt output signal which may be applied to and used by the interrupt receiving device.
Within conventional digital video processors it is known to clock different elements within the video processor at different clock rates. Therefore, a received clock signal may be divided down to provide a clock signal having a different clock rate. Because the clock signal provided in this manner is a divided down clock it does not matter under normal circumstances what its phase may be with respect to the received clock. Furthermore, this divided down clock is strictly an internal clock and is not available external to the video processor. Therefore, the divided down clock may normally operate at a random phase with respect to the received clock. However, the existence of a clock at an unknown phase with respect to the internal clock may, in certain circumstances, make testability of certain operations of the digital video processor more difficult.
When access to a page of memory is complete and access to a different page is begun, the completed page must be closed and the new page must be opened. It is well known to those skilled in the art that the time for a video processing system to obtain access to a page of memory which is not open exceeds the access time required for access to the same page if the page is open. Furthermore, the access time required to access a different page of memory when a current page is open is even longer. Therefore, it would be more efficient to know whether the next access is in the same page in order to determine whether to close the current page when the system accesses memory VRAM.